The present disclosure relates generally to information handling systems, and more particularly to detecting link downgrades in endpoint devices used in information handling systems.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Many information handling systems include peripheral devices that may be connected to the information handling system via a motherboard. For example, network cards, video cards, port expansion cards, storage devices, and other peripheral devices may be coupled to the motherboard using high-speed serial links in order to enhance the capabilities and performance of the information handling system. Peripheral Component Interconnect Express (PCIe) is a standard for such high speed serial links between the motherboard and the peripheral device, and provides for communication between PCIe devices via a logical connection called a link, which is a point-to-point communication channel between two PCIe ports that allows for the sending and receiving of ordinary PCIe requests and interrupts. At the physical level, a link is composed of one or more lanes, and a lane is composed of two differential signaling pairs, with one pair utilized for receiving data and the other pair utilized for transmitting data. Thus, each lane is composed of four wires or signal traces. Conceptually, each lane is used as a full-duplex byte stream, transporting data packets in eight-bit “byte” format simultaneously in both directions between endpoints on a link. Physical PCIe links typically contain from one to 32 lanes and, more precisely, 1 lane, 2 lanes, 4 lanes, 8 lanes, 12 lanes, 16 lanes, or 32 lanes, and PCIe links typically operate at transfer rates of 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s, or 32 GT/s.
During a power-on self-test (POST) operation performed by a Basic Input/Output System (BIOS), the BIOS may access a link capabilities register that is included on a PCIe device and that advertises the Maximum Link Speed (MLS) and a Maximum Link Width (MLW) for the PCIe device, as well as a link status register that is included on the PCIe device and that advertises a Current Link Speed (CLS) and a Negotiated Link Width (NLW) for the PCIe device. In a conventional BIOS, if one of the CLS is less than the MLS, and/or the NLW is less than the MLW, then the BIOS reports a downgrade of the PCIe link to a user, which may indicate to the user that the PCIe device is not functioning properly. However, some PCIe devices may intentionally reduce link width or link speed as a power saving measure when it is not necessary to have both a maximum link speed and a maximum link width to achieve a desired level of performance (e.g., an optimal level of performance.) As such, the conventional BIOS may report that the PCIe link is downgraded even though the PCIe device is in a reduced power state that still maintains the desired level of performance for the PCIe device. Thus, users may receive the downgrade notification for that PCIe device operating at the desired level of performance while in the reduced power state mode, and begin troubleshooting procedures when there is no need to do so. In other instances, repeated downgrade notifications resulting from the above issues may cause a user to ignore a downgrade notification that is a result of reduced performance of the PCIe device and/or the device to which the PCIe device is attached.
Accordingly, it would be desirable to provide an improved link downgrade detection system.